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GL3590
產品簡述

Genesys GL3590 is a low-power, and configurable USB 3.1 Gen 2 hub controller. It is compliant with the USB 3.1 specification. GL3590 integrates Genesys Logic self-developed USB 3.1 Gen 2 Super Speed transmitter/receiver physical layer (PHY) and USB 2.0 High-Speed PHY. It supports Super Speed, Hi-Speed, and Full-Speed USB connections and is fully backward compatible to all USB 2.0 and USB 1.1 hosts. GL3590 also implements multiple TT architecture providing dedicated TT to each downstream (DS) port, which guarantees Full-Speed(FS) data passing bandwidth when multiple FS devices perform heavy loading operations.

 

GL3590 features the native fast-charging and complies with USB-IF battery charging specification rev1.2. With different configurations, it could fast-charge Apple devices with up to 2.4A, Samsung Galaxy devices, and any device complaint with BC1.2/1.1. It also allows portable devices to draw up to 1.5A from GL3590 charging downstream ports (CDP) or dedicated charging port (DCP). It can enable systems to fast charge handheld devices even during “Sleep” and “Power-off” modes.

 

  • Compliant with USB 3.1 Specification
    • Upstream port supports SuperSpeed+ (10G/SS+), SuperSpeed (5G/SS), HighSpeed (HS) and FullSpeed (FS) traffic
    • Downstream ports support SS+, SS, HS, FS, and LowSpeed (LS) traffic
    • 1 control pipe and 1 interrupt pipe
    • Backward compatible to USB specification Revision 2.0/1.1
  • Native USB USB-C/Power delivery support in GL3590-S series
    • Compliant with USB Type-C™ Cable and Connection Specification Revision 1.0
    • Compliant with Power Delivery spec rev. 3.0
    • Support TCPC interface; compliant with Type-C™ Port Controller Interface Spec 1.0
    • Support up to 2-port Power Delivery 3.0
    • Support up to 4-port native USB Type-C ports, no external Mux or CC controller needed
    • USB-C port supporting USB-C current modes , including USB Default, 1.5A@5V, 3A@5V
  • On-chip 8-bit micro-processor
    • RISC-like architecture
    • USB optimized instruction set
    • 1 cycle instruction execution (maximum)
    • Performance: 12 MIPS @ 12.5MHz (maximum)
    • With 256-byte RAM, 20K-byte internal ROM, and 64K-byte SRAM
  • Multiple Transaction Translator (TT) architecture
    • Providing dedicated TT control logics for each downstream port
    • Superior performance when multiple FS devices operate concurrently
  • Integrated USB transceiver
    • Improving output drivers with slew-rate control for EMI reduction
    • Internal power-fail detection for ESD recovery
  • Advanced power management and low power consumption
    • Supporting USB 3.1 U0/U1/U2/U3 power management states
    • Supporting USB Link Power Management (LPM) L0/L1/L2
    • Supporting individual/gang mode over-current detection for all downstream ports
    • Supporting both low/high-enabled power switches
    • Patented Smart Power Management
  • Configurable settings by firmware
    • Configurable downstream ports, downstream port can be disabled/enabled by each specific port for USB3.1/USB2.0
    • Configurable Upstream and Downstream Ports in GL3590-S
    • Configurable charging port
    • Supporting full in-system programming firmware upgrade by SPI-flash
    • Supporting compound-device (non-removable setting on downstream ports)
    • Supporting customization VID/PID
  • Flexible design
    • Supporting Poly-fuse/Power-switch
    • Automatic switching between self-powered and bus-powered modes
    • Supporting electrical tuning for each specific port
    • Supporting programmable breathing LED
    • Supporting register setting by firmware
    • Supporting vendor command and SMBUS
    • Multiple upstream port supported in GL3590-S
    • Host bridge hardware engine implemented in GL3590-S for KM applications
  • Featuring fast-charging on all downstream ports and upstream port
    • Compliant with USB Battery Charging Revision v1.2, supporting CDP, DCP, and ACA-Dock
    • Downstream ports can be turned from a Standard Downstream Port (SDP) into Charging Downstream Port (CDP) or Dedicated Charging Port (DCP)
    • Downstream devices can be charged while upstream VBUS is not present, which can be applied on wall charger applications
    • Upstream port is capable of charging and data communicating simultaneously for portable devices supporting ACA-Dock or proprietary charging protocols
    • Supporting Apple 1A/2.1A/2.4A and Samsung Galaxy devices fast-charging
  • Low BOM cost
    • Single external 25 MHz crystal / Oscillator clock input
    • Built-in upstream port 1.5KΩ pull-up and downstream port 15KΩ pull-down resistors
  • Different package types available for various applications
  • Applications
    • Standalone USB hub/Docking station
    • Motherboard
    • Monitor built-in hub, GPIOs can be programmed as I2C interface to easily update scalar firmware through USB interface
    • TV built-in hub
    • KM application
    • Customized applications
      • Dynamically disable/enable ports
      • GPIO signaling of ambient light sensor or rotation/position sensor

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